In recent years, advanced micro-electronic devices are fabricated with very large scale integration (VLSI) or ultra large scale integration (ULSI) techniques such that extremely complex electrical circuits can be fabricated onto a very small chip. The large reduction in size of the micro-electronic devices requires the development of new design and manufacturing technologies to accomplish the miniaturization of such semiconductor devices. One of the critical fabrication steps for the micro-electronic devices is the photolithographic process in which a pattern of the circuits in a microscopic scale is transferred from a photomask onto a wafer surface such that the circuits are reproduced on the wafer.
A typical photolithographic process utilizes a step-and-repeat process to gradually transfer a mask pattern to a chip implementation on a microscopic scale. The process involves many individual steps of reductions wherein errors may be introduced into the final mask. For instance, in such a micro-lithography process, problems exist in the accurate measurement of overlay which is an indication of the degree of misalignment between successive layers of patterns on a semiconductor wafer surface and of the alignment of a mask/reticle pattern for printing such layers to preceding layers. In conducting lithography on such a microscopic scale, the capability of making an accurate measurement of overlay is a critical requirement of the process.
In a conventional method for measuring overlay and for aligning the wafers, a global alignment method and global alignment marks are frequently utilized wherein alignment marks are patterned by an independent process layer and then all the other device process layers are aligned to the alignment marks. For the device layers, the degree of overlay shift (or error) can be measured by specifically designed measurement patterns from both successive and preceding layers formed by scribe lines for checking the overlay. However, as the device dimensions continue to become miniaturized, the accuracy achieved by a conventional method for overlay measurement becomes inadequate due to its poor resolution and accuracy. For instance, in a 0.25 .mu.m design rule, the overlay specification must be in the range of approximately 0.025 .mu.m. The microscopic measurements should be conducted by a SEM (scanning electronic microscopy) or AFM (atomic force microscopy) method in order to verify the overlay accurately.
In the conventional measurement techniques, a wafer overlay measurements can be conducted by a box-in-box or critical dimension (CD) technique in which tests mask targets are placed at different areas of the wafer surface. For instance, the test targets can be laid out in the peripheral regions on a wafer surface. The measurements are then conducted to verify the accuracy of the circuit lay out by comparing shifts in the box center lines to a process average. With the conventional techniques, an accurate wafer dimensional quality determination cannot be made until box-in-box targets are made on an appropriate number of cells within a circuit. Furthermore, in the conventional measurement techniques, by using a stepper machine, a focal plane of the stepper is determined manually by technicians by visually reading exposed 0.6 .mu.m focus matrix dots. The process is repeated until a satisfactory focal plane is determined as the center of focus when a good resolution of the 0.6 .mu.m dots is obtained. The disadvantages of this technique is the large focus error caused by the manual reading taken by different technicians. A typical accuracy that can be obtained with this method is 0.2 .mu.m which is inadequate for the mass production of sub-half micron technology devices.
It is therefore an object of the present invention to provide a pattern for stepper focus that is monitored by an overlay measurement without the drawbacks and shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming a stepper focus pattern that can be monitored by an overlay measurement and be suitably used in the mass production of sub-half micron technology devices.
It is a further object of the present invention to provide a method for forming a stepper focus pattern that can be used to accurately measure a misalignment that is sensitive to focus change.
It is still another object of the present invention to provide a method for forming a stepper focus pattern for determining a focal plane accurately and for reducing the focus error caused by a manual reading method.
It is yet another object of the present invention to provide a method for forming a stepper focus pattern in which a plot of the overlay values versus the focus lengths can be obtained to produce a focal plane by an overlay value calculated.
It is another further object of the present invention to provide a method for forming a stepper focus pattern in which a formula is provided for the accurate determination of an overlay error between an inner box and an outer box alignment marks.